-------------------------------------------------------------------------------
-- Title      : 
-- Project    : 
-------------------------------------------------------------------------------
-- File       : sequencer.vhd
-- Author     :   <Rome@ROME-PC>
-- Company    : 
-- Created    : 2014-03-11
-- Last update: 2014-03-11
-- Platform   : 
-- Standard   : VHDL'87
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Copyright (c) 2014 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2014-03-11  1.0      Rome    Created
-------------------------------------------------------------------------------

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sequencer is
  
  generic (
    RESET_CNT : integer := 100000);

  port (
    clk_sys_i   : in  std_logic;
    rst_ext_n_i : in  std_logic;
    rst_n_o     : out std_logic);

end sequencer;

architecture behave of sequencer is

  signal cnt_rst : integer   := 0;
  signal rst_n_l : std_logic := '0';
  
begin  -- behave

  rst_n_o <= rst_n_l;

  process (clk_sys_i, rst_ext_n_i)
  begin  -- process
    if rst_ext_n_i = '0' then           -- asynchronous reset (active low)
      cnt_rst <= 0;
      rst_n_l <= '0';
    elsif clk_sys_i'event and clk_sys_i = '1' then  -- rising clock edge
      if cnt_rst /= RESET_CNT then
        cnt_rst <= cnt_rst + 1;
        rst_n_l <= '0';
      else
        cnt_rst <= cnt_rst;
        rst_n_l <= '1';
      end if;
    end if;
  end process;

  process (clk_sys_i)
  begin  -- process
    if clk_sys_i'event and clk_sys_i = '1' then  -- rising clock edge

    end if;
  end process;

end behave;
